1. Field of the Invention
The present invention relates to a duty ratio correction circuit and a duty ratio correction method.
2. Description of Related Art
A memory interface is becoming increasingly faster with the recent trend towards higher-speed and lower-voltage operation of an application-specific integrated circuit (ASIC), a microprocessor or the like. Particularly, in double-data-rate (DDR) mode, the deviation of the duty ratio of a clock which is fed into a circuit is a contributing factor to degradation of the setup/hold characteristics. Japanese Unexamined Patent Application Publications Nos. 2002-190196 and 2007-121114 disclose a method of correcting a clock duty ratio.
Further, the deviation of the duty ratio of an asynchronous signal such as data or address due to the characteristics of an input circuit or another circuit is also a contributing factor to degradation of the setup/hold characteristics, just like the case of a clock. Japanese Unexamined Patent Application Publications Nos. 2006-012363 and 2006-013990 disclose a technique of correcting the amount of data delay.
FIG. 8 is a view to describe a concern of the present invention, which shows an example of a clock duty ratio correction circuit. The duty ratio correction circuit includes an input buffer 1 for data, an input buffer 2 for clock, a duty adjuster 4, a duty comparator 5, and a latch circuit 6.
The data input buffer 1 converts an external data signal IN_EX into an internal data signal IN. The internal data signal IN is then input to the latch circuit 6.
The clock input buffer 2 shapes the waveform of an external clock signal CLK which is input from the outside of a semiconductor storage device and converts it into a signal level to be used inside the semiconductor storage device. The clock input buffer 2 then outputs a clock signal P_CLK.
The duty adjuster 4 corrects the duty ratio of the clock signal P_CLK which is output from the input buffer 2 based on a potential signal DUTY_DC which is fed back from the duty comparator 5. The duty adjuster 4 then outputs an internal clock signal IN_CLK to the latch circuit 6 and the duty comparator 5.
The duty comparator 5 monitors the duty ratio of the internal clock signal IN_CLK and integrates the deviation of the duty ratio in each cycle. The duty comparator 5 then outputs the potential signal DUTY_DC. In such a configuration, the duty ratio of the internal clock signal IN_CLK can be corrected.
FIG. 9A shows an ideal waveform of the external data signal IN_EX with respect to the external clock signal CLK. The external data signal IN_EX is input such that it is VALID during the period of the setup time (TS) and the hold time (TH) which are described in the data sheet or the like with respect to the external clock signal CLK.
Specifically, the external data signal IN_EX(H) changes like “L, H, L” in order that it is H during the period of the setup time TS and the hold time TH. On the other hand, the external data signal IN_EX(L) changes like “H, L, H” in order that it is L during the period of the setup time TS and the hold time TH.
The internal clock signal IN_CLK and the internal data signals IN(H) and IN(L) in FIG. 9B show signals at the point where the external clock signal CLK and the external data signals IN_EX(H) and IN_EX(L) in FIG. 9A have passed through the input buffer 1 or 2 or the like and reached the latch circuit 6.
The deviation between the time when the internal data signal IN(H) changes from H to L and the internal data signal IN(L) changes from L to H is referred to as a duty deviation time TD. As shown in FIG. 9B, by passing through the input buffer 1 or the like, the hold time TH with respect to the internal clock signal IN_CLK is degraded by the length of the duty deviation time TD of data. Therefore, it is necessary to correct the duty ratio of data or address also as described above.
However, there is a concern that the duty adjuster 4 and the duty comparator 5 for clock cannot be used for an asynchronous signal such as data or address. The reason is described hereinbelow.
Provided that an asynchronous signal such as data or address satisfies the setup time and the hold time which are described in the data sheet or the like with respect to the external clock signal CLK, the asynchronous signal may have a signal level of either H or L in the other times.
Therefore, in the case where the internal data signal IN changes like “L, L, H” with respect to the external clock signal CLK as shown in FIG. 10, for example, the duty ratio of a signal with a cycle of T_IN is adjusted even if there is no deviation of the duty ratio due to the input buffer 1 for data. In such a case, the duty ratio is wrongly determined to be 1/3=33%, which is low.